叁维封装的可靠性工程

By the end of this full project, the following deliverables will be ready along with the samples of 3D packages: • Deliver a patentable PoP module with a warpage reduction of at least 50% and a stand-off height of 0.4mm vs. the existing PoP module using the developed virtual packaging design advisor (due by 31/12/2009); • Design documents and samples of stacked 3D system with a dimension of 12x12x3mm3 or less, including multi-functional chips (e.g., 1 digital, 1 RF, 4 memory, etc.) integrated using mixed interconnect technologies (e.g., WB, FC, TSV) (due by 30/06/2010); • Full set of validated key manufacturing process simulation models (i.e., molding, reflow, and underfill, etc.) for PoP-based 3D packages (due by 31/03/2009); • Full set of validated key manufacturing process simulation models (i.e., via drilling, via filling, and die bonding, etc.) for TSV-based 3D packages (due by 31/12/2009); • Full set of validated key reliability test simulation models (i.e., TC, humidity, preconditioning, and drop test, etc.) for PoP- and TSV-based 3D packages (due by 30/09/2009); • Demonstrate the functionalities of virtual packaging design advisor (e.g., process and reliability models, DFM and DFR guidelines, experimental techniques) for 3D packaging products/applications (due by 22/03/2010); • File at least four patents (due by 31/12/2009); • Technical reports on 3D packaging development status and trends, including worldwide 3D packaging related activities by key universities, RIs (Research Institutes) and MNCs (Multi-Nation Companies), patent mapping/strategy, market status and major applications (due by 31/03/2009).