交付项目:
a) A verified 0.18um test chip with BLE RF transceiver IPs blocks including Low Noise Amplifier (LNA), mixer, switched capacitor (SC) filter, digital Phase Locked Loop (PLL) and Power Amplifier (PA), BLE digital baseband IPs and BLE SoC peripheral IPs including oscillators, watchdog timer, low dropout regulator, power-on reset, temperature sensor, bandgap reference, 13-bit ADC, SPI and UART. b) An analogue PLL verilog model customized for Sytrons = contract service deliverable. c) A verified 0.18um BLE SOC engineering prototype which integrates the BLE RF transceiver, BLE digital baseband and BLE SOC peripheral IPs for stand-alone products. d) A verified 65nm test chip with BLE RF transceiver IPs blocks including Low Noise Amplifier (LNA), mixer, switched capacitor (SC) filter, digital Phase Locked Loop (PLL) and Power Amplifier (PA), BLE digital baseband IPs and BLE SOC peripheral IPs including oscillators, watchdog timer, low dropout regulator, power-on reset, temperature sensor, bandgap reference, 13-bit ADC, SPI and UART. e) A verified 65nm BLE SOC test chip which integrate the BLE RF transceiver, BLE digital baseband and BLE SOC peripheral IPs for combo chip applications. f) PCB demo module for testing the SOC communication with TI’s BLE SOC as a reference design including a subset of software protocol
研究团队:
Ms Karen Wan
Mr Bryce Yau
Mr Andy Wu
Dr Zuqiang Tang
Mr Xiaoxiang Li
Mr Tat Fu Chan
Mr K C Wan
Ms Gigi Chan
Mr Henry Chiu
Mr K C Au
Mr Jacky Cai
Mr Jeff Wong
Mr Daniel Wong
Mr Edward Wong
Ms Sidar Lai
Mr Eric Chan
Ms Zoe Mak
Mr Kai Man Ho
Mr Johnny Chan
Mr Ka Hung Kwok
Mr Yat Tung Lai
Mr Zhongliang Zhou
描述:
本項目提出一個用於低功耗藍牙(BLE)無線體域網(WBAN)的超低功率射頻IPs 與系統芯片平台。目的是開發一個低功耗藍牙(BLE)系統芯片。它包括身體傳感器網絡IPs,射頻收發器,數字基帶及BLE的協議棧一部分。該系統芯片可開發創新WBAN應用示範模塊。該項目為期18個月，預算為14.689M。承諾的業界贊助是1.694M。它為本當地業界發展前沿WBAN產品提供了堅實的基礎和基本模塊。它具有顯著的商業潛力和社會效益。
