立體圖像信號處理器

Algorithms Design • Depth estimation & Video format conversion IPs and corresponding documentation • Performance and simulation models for depth estimation & Video format conversion Reference IC Implementation • Frontend logical database(RTL) in Verilog format • Physical layout in GDSII format • Reference IC with processor core and peripherals • Hardware spec, Implementation and verification documents Development Platform • FPGA development board for IP verification • Reference IC test board and development platform