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Smart Appliances Transceiver

Project Title:
Smart Appliances Transceiver
Project Reference:
ART/159CP
Project Type:
Project Period:
20130725 - 20150824
Funds Approved (HK$’000):
12292
Project Coordinator:
Mr Yiu-kei Li
Deputy Project Coordinator:
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Deliverable:
Develop RX/TX algorithms A1) Survey report of existing algorithm and preliminary ASTRI's algorithm development (Completed at Month 7) A2) Report of ASTRI's algorithm with performance simulation models (Completed at Month 15) Hardware Architecture B1) Top-Level architecture specification of Homeplug Green PHY(HPGP) SoC (Completed at Month 9) B2) Microarchitecture specification of HPGP functional modules (Completed at Month 12) Implementation of HPGP algorithms on ASIC silicon C1) Full reference system demonstrating HPGP connectivity using MPW test chip (Completed at Month 21) C2) Evaluation Report of HPGP test chip ASIC (Completed at Month 21) Software Development on Evaluation Platform D1) Demo software on evaluation platform (Completed at Month 10)
Research Group:
Mr Alan Cheung Mr Gordon Chung Mr Patrick Kong Dr Chi Hong Chan Mr Chi Lok Tsui Mr Yu Song Mr Hongzao Chen Mr Gordon Yu Dr Man Chi Chan Ms Carina Huang Ms Rita Cheng Ms Winki Yeung Mr Peter Cheng Mr James Ning Mr Walter Chow Dr Yuzhong Jiao Mr Teddy Wong Mr Yun Kau Lee Mr Mark Mok Mr King Hung Chiu Mr Boson Lin Mr Chan Fai Lam Mr Jingwei Liu Mr Bingao Qiu Ms Cindy Tang Mr Kwok Kwan Tong Mr Ka Lung Wong Ms Zhixia Zhu
Sponsor:
HiSilicon Technologies Co. Ltd. Jinan Superspeed Semiconductor Ltd. [Sponsor]
Description:
This project aims to develop IC technology to perform powerline communication based on the HomePlug Green PHY standard. With rising energy costs, the need for smart energy and variable utility rates is inevitable. The objective is to create intellectual property (IP) blocks to enable smart appliances as part of smart energy ecosystem. The research methodology follows the stages of algorithm development, hardware architecture definition and system implementation. The developed silicon will contain blocks including analog front end (AFE), physical layer (PHY) and media access layer (MAC). Research will involve algorithms for robust data synchronization and improved security. Another key feature of this project is the inclusion of a built-in energy monitor. When the project is completed, the technology developed will allow IC manufacturers and appliance makers to offer connectivity and smart energy features to traditional appliance applications. Working in tandem with the smart grid, the peak energy consumption can be managed leading to lower cost of energy for utilities and reduced need for generation capacity. The results will have strong economic and environmental impact for both individuals and society at large.
Co-Applicant:
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Keywords:
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