Project Title:
Feasibility study of a DDR4 analog PHY’s architectural design with industry standard DFI bus interface
Project Reference:
ARD/120
Project Period:
20130220 - 20130819
Funds Approved (HK$’000):
1980
Project Coordinator:
Mr David Kwong
Deputy Project Coordinator:
/
Research Group:
Dr K C Wang
Mr Simon Lee
Mr Andy Wu
Ms Jennifer Ho
Mr Ka Hung Kwok
Mr K C Au
Mr K C Wan
Ms Sidar Lai