Cross Platform IO Design For FinFET Technology (ART/273CP) | ASTRI - Hong Kong Applied Science And Technology Research Institute Company Limited

Project Title:

Cross Platform IO Design for FinFET Technology (ART/273CP)

Project Reference:

ART/273CP

Project Type:

Platform

Project Period:

16 / 03 / 2019 - 15 / 03 / 2021

Funds Approved (HK$’000):

12,414

Project Coordinator:

Dr Beiping YAN

Deputy Project Coordinator:

Deliverable:

Milestone1: 14nm IO library design, including: 1a) 14nm IO schematic design, simulation results, layout & tape out; 1b) design kits; 1c) testing/evaluation report. Milestone2: 110nm IO library design, including: 2a) 110nm IO schematic design, simulation results, layout & tape out; 2b) design kits; 2c) testing/evaluation report. Milestone3: Cross platform IO design (internal use, not for licensing), including: 3a) cross platform layout automatic generation technique; 3b) cross platform design kits generation technique. Milestone4: Cross platform IO library verification, including: 4a) cross platform IO verification/tape-out in FinFET technology; 4b) cross platform IO verification/tape-out in planar process.

Research Group:

Sponsor:

CSMC Manufacturing Co. LTD (Technology Licensing) [Sponsor]
CSMC MANUFACTURING Co., LTD [Sponsor]
eTownIP Microelectronics （Beijing）Co., LTD [Sponsor]
eTownIP Microelectronics （Beijing）Co., LTD (Technology Licensing) [Sponsor]

Description:

IO (input/output) is the fundamental building block of integrated circuits (ICs). Without IO, ICs cannot implement their functions. Usually, IO is process dependent, difficult to be converted to other process platforms. From technology and market perspective, IC industry has a strong desire to develop cross platform IO to support different process platforms and EDA tools. Furthermore, IO must be with low parasitic capacitance, high ESD capability, and small area, because IC's performance (speed, reliability, and density) is determined by them.

This project targets at developing cross platform IO design for FinFET technology, with reduced area and enhanced speed. Through the cross-platform algorithm, the IO to support different process platforms and EDA tools will be developed. Speed enhancement, high reliability and reduced area will be achieved by a low-cap ESD design and innovative clamp circuit. The cross-platform IO technology developed from this project will be verified in different foundries.

The success of this project would bring a technical breakthrough in IO design. The IO libraries to support different platforms could be produced quickly, which would have an impact on regional and global IO market.

Co-Applicant:

Keywords:

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Hong Kong Applied Science and Technology Research Institute (ASTRI) was founded by the Government of the Hong Kong Special Administrative Region in 2000 with the mission of enhancing Hong Kong’s competitiveness through applied research. ASTRI’s core R&D competence in various areas is grouped under five Technology Divisions: Advanced Electronic Components and Systems; Artificial Intelligence and Trust Technologies; Communications Technologies; Innovative Mind; and IoT Sensing and AI Technologies. It is applied across six core areas which are Smart City, Financial Technologies, New Industrialisation and Intelligent Manufacturing, Digital Health, Application Specific Integrated Circuits and Metaverse.

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